What is Universal Verification Methodology

The universal verification methodology is a standard comprehensive method for verifying integrated circuit design. Initially, open verification methodology was mainly used for ascertaining language which large part was based on eRM (e Reuse Methodology) developed by varsity design in 2001.

According to information from the Universal Verification Methodology library there exist a significant difference when compared to other previous methodology developed independently by the simulator vendors for it bring much computerization to the SystemVerilog language such as data automation features and sequence (packing, compare, copy). Also, it is an Accellera standard supported by multiple vendors such as Graphics, Cadence, Aldec, Synopsys and Mentor.


In December 2009 a technical subcommittee of a standard organization in the electronic design automation industry known as (Accellera) voted to establish UVM basing the new standard on Open Verification Methodology. Open Verification Methodology was jointly developed in 2007 by cadence design system and Mentor Graphics. Accellera approved the 1.0 version of UVM on 21 February 2011. The version includes the Reference guide, a Reference implementation of the form of a SystemVerilog base class liberally and a user guide.

Objective Oriented Concept

Mainly the UVI is a methodology for functional verification of digital hardware primary using simultaneously. Verilog or SystemVerilog is used to describe the hardware or system to be verified at any appropriate abstraction level.

Objective Oriented Concept

This could be gate level, behavior level or register transfer level. It can be used in assertion-based verification, hardware acceleration or emulation although UMI is highly explicitly simultaneous oriented.

• Sequence: an ordered collection of transactions. Sequences are assembled from transactions and are used to build realistic sets of stimuli. Every course contains a body task which when executed it generates those transactions or runs other sequences. The sequence represents a class of dynamic data within the verification mode.
• Monitor: a monitor is a variety of that is confirmed to have large signal access to the signal level interface of the DUT. Monitors traffic going on and from the DUT. Assembles transactions which are distributed to the rest of the verification environment through one or more analysis port.

The uvm courses

The uvm courses are responsible for the following three main functions
• Put the Design Under Verification(DUV) and verification environment into an initialization state.

Configure the verification environment and Design Under Verification. The entire Design Under Verification scenario generation.


At this stage Device Under Test and the environment, it is it should be set to the condition required before simulation. This include
• Pin setting on the DUT, such as power and high impedance.
• Loading memory, with any needed initial conditions
• Verification components settings that cannot be altered during simulations process example the mode bits or if part of the environment registration.
• Verification component settings that can’t be altered during the simulation process.

Design Under Verification(DUV)

Benefits of UVM

• Enables multiple language plug and play VIP
• Delivers an open, unified class liberally and methodology for interoperable VIP
• Support module to system and project to project reuse.
• Provide built-in automation and test bench capabilities
• Includes methodology user guide and reference documents
• Eliminates the need for interop ability among multiple verification libraries


Universal Verification Methodology is a capable and rich class library that has evolved from much experience with real verification projects, and SystemVerilog is a large and complex language. As a result, even though UVM provides compelling features for verification experts, it’s a challenge to Verilog designers who want to benefit from test bench reuse.